Field of the Invention
The invention relates to a processor with a pipelining structure, in particular with a superscalar architecture, having a configurable logic unit, an instruction memory, a decoder unit and an interface device. The invention also relates to a method for high-speed calculation with pipelining processors.
Such microarchitectures are intended to achieve the maximum degree of parallelity at the instruction level in microcomputers.
Central arithmetic units in microcomputers mainly are formed of the processor, which should be regarded as an autonomous processor in the following text, for example as a microprocessor which is not part of a microprocessor system or for which that association is irrelevant for the purposes of instruction parallelity.
In general the processors are constructed on the basis of the von Neumann model. While that model has been dispensed with for separation of code and data storage area in the Harvard model (those storage areas are separated there and accessed by using different access routes), the strict processing and result sequencing of the command flow is applicable both in the von Neumann model and in the Harvard model with its many modifications and variants. Data flow computers, which operate with control by the data flow rather than by the control flow, represent exceptions to that model.
While retaining the sequential processing of the command flow, the introduction of so-called RISC architectures, which initially contained only a reduction in the instruction set to simplify the processor structure, has produced an increase in speed to one command per processor system clock cycle. That has been achieved by replacing a microprogram in the processor by hard-wired hardware and by extensive pipelining measures. Despite apparent parallelity within the processor, the maximum command rate, with one instruction per clock cycle, and the processing and result sequencing, have been maintained.
With regard to the prior art, U.S. Pat. No. 5,361,373 which describes a dynamically configurable gate array, as well as a publication entitled "High Performance Computing Using A Reconfigurable Accelerator" in "CONCURRENCY: Practice and Experience, Vol. 8 (6), 429 443 (July-August 1996)", should also be mentioned. The latter describes a pure coprocessor, which includes a reconfigurable arithmetic-logic unit (rALU) that is completely loaded at the start of the program (!) so that particular loops in a program can be processed quickly. That necessitates a high level of compiler complexity. Due to the complete capability to write to it, such an arithmetic unit has considerably more complex commands. Recompiling is tedious.